1. Field of the Invention
The present invention is directed to densely packed vertical transistors in a 4F-square memory cell, and methods for making thereof, and more particularly, to memory cells having self aligned sources with deep trench capacitors formed in trenches that separate the vertical transistors.
2. Discussion of the Prior Art
There is much interest to scale down densely packed semiconductor devices on an integrated circuit (IC) chip to reduce size and power consumption of the chip, and allow faster operation. In order to achieve the high packing density necessary for GBit memory applications, it is crucial to shrink the size of an individual memory cell as much as possible. FIG. 1 shows a top view of a conventional array 10 of conventional erasable programmable read only memory (EPROM) devices 15, using vertical transistors, such as metal oxide silicon field effect transistors (MOSFETs) with a floating gate layer. The conventional array 10 is described in the following two references. H. Pein and J.D. Plummer, "A 3-D sidewall flash EPROM call and memory array", Electron Device Letters, Vol. 14 (8) 1993 pp.415-417. H. Pein and J.D. Plummer, "Performance of the 3- D Pencil Flash EPROM Cell and Memory Array", IEEE Translations on Election Devices, Vol. 42, No. 11, 1995, pp. 1982-1991.
The conventional array 10 has rows of wordlines 20 and columns of bitlines 25. The size of a cell 27 of the array 10 is 2F by 2F+.DELTA., leading to a cell area of 4F.sup.2 +2F.DELTA.. F is the minimum line width of the feature size that can be patterned with lithography. 2F is the cell size along the wordline 20, and 2F+.DELTA. is the cell size along the bitline 25. Typically, .DELTA. is approximately 0.2-0.5F, resulting in a cell area of approximately 4.4-5.0F.sup.2 area achievable using conventional lithography. The additional length .DELTA. is necessary to separate adjacent wordlines 20.
FIG. 2 shows a partial perspective view of the array 10 of FIG. 1, and FIG. 3 shows a cross sectional view of the vertical MOSFET 15 along a bitline 25.
As shown in FIG. 3, the MOSFET 15 has an n.sup.+ source 30 formed on a P-doped silicon substrate 35. The source 30 is formed after etching the substrate 35 to form a vertical pillar 40, referred to as the body of the MOSFET 15. The pillar 40 acts as the transistor channel and has dimensions of F by F, as shown in FIGS. 1 and 3.
As a result of forming the source 30 after forming the pillars 40, the source 30 is formed around edges of the pillar 40 and is absent from a region 45 located below the pillar 40. Thus, the source 30 does not entirely occupy the footprint or lower portion of the pillar 40. As shown in FIG. 2, all the MOSFETs 15 of the array 10 have a common source 30, including MOSFETs of different bitlines 25 and different wordlines 20. As shown in FIGS. 2-3, the top of each pillar 40 is doped with N-type material to form n.sup.30 drains 50 of the vertical transistors 15.
tunnel oxide 60 is formed around the pillar 40 and an oxide spacer 65 is formed on the source 30. Next, a polysilicon floating gate 70, gate oxide 75 and olysilicon control gate 20 are formed around the tunnel oxide 60. Note, control gates 20 of individual transistors along the wordline 20 are interconnected to form the wordline 20.
Because the polysilicon control gate 20 grows uniformly around each vertical MOSFET 15, the spacing between MOSFETs 15 of adjacent rows is slightly larger than the feature size F, e.g., F+.DELTA., where a is approximately 0.2F. This separates adjacent wordlines 20 by amount .DELTA., when polysilicon is grown up to a distance of 0.5F. This 0.5F thick polysilicon layer covers the top and sidewalls of the pillars 40, as well as the oxide spacer 65 located on the substrate 35 at the base of the pillars 40.
The 0.5F thick grown polysilicon regions at pillar sidewalls separated by distance F, along each wordline 20, merge with each other. This forms the wordlines 20 around a row of pillars that are separated by F. However, the 0.5F thick formed polysilicon regions at pillar sidewalls separated by distance F+.DELTA. do not merge. Rather, they remain separated by the distance .DELTA.. At the base of the trenches located between these polysilicon-covered pillar sidewalls that are separated by F+.DELTA., the oxide spacer 65 is covered with the 0.5F thick polysilicon.
To separate adjacent wordlines 20, an anisotropic reactive ion etch (RIE) is performed that removes polysilicon for a thickness of 0.5F vertically only. The RIE exposes the top of the pillars 40, as well as the oxide spacer 65 at the base of the pillars that are separated by F+.DELTA., leaving a sidewall of polysilicon on the edge of each pillar. The exposed distance of the oxide spacer 65 is .DELTA.. Thus, the .DELTA. separation between adjacent wordlines 20 ensures that control gates 20 of adjacent wordlines are not shorted along the direction of the bitlines 25.
As shown in FIGS. 1 and 2, a first level metal forms bitlines 25 which are orthogonal to the wordlines 20. The first level metal connects drains 50 of MOSFETs 15 along a common bitline 25. The area of the cell 27 of FIG. 2, is small because the substrate 35 is used as a common source 30 for all the MOSFETs 15 of the array 10.
FIG. 4 shows a three-dimensional view of another conventional array 90, which is similar to the conventional array 10 of FIG. 2, except for having round pillars 95 instead of square pillars 40 (FIG. 2). As in the array 10 of FIG. 2, the array 90 of FIG. 4 has a common source 30.
The memory function of each cell 27 (FIGS. 1, 2)is achieved by charging or discharging the floating gate region 70. This causes a measurable shift in the threshold voltage of the vertical MOSFET.
However, to make the conventional MOSFETs 15 useful for DRAM applications, the cell must be modified to isolate the source regions 30 between adjacent bitlines 25. Furthermore, to achieve the packing density necessary for GBit memories, the overall cell area must not be increased by these modifications. The cell area must remain approximately 4F-Square.
One method for achieving source isolation between bitlines 25 is to pattern isolation lines lithographically between the bitlines 25. Isolation is then achieved by either a local oxidation of silicon (LOCOS), recessed-LOCOS, or conventional shallow trench techniques.
However, such an isolation method requires lithography. Therefore inter-device 20 lines must be increased from F to at least 2F to avoid shorting adjacent control gates, or wordlines 20 along the bitlines. This increases the inter-device spacing along the bitlines 25 from 1.2F to 2F. Thus, the overall cell size increases from 4F.sup.2 +0.4F to at least 6F.sup.2. Moreover, lithographic misalignment degrades device behavior. Hence, packing density and/or performance is sacrificed in this scheme.
To increase packing density, instead of forming the vertical MOSFET 15 having the pillar 40, an inverted transistor is formed in a trench etched into the substrate. Such transistor structures are shown in U.S. Pat. Nos. 5,386,132; 5,071,782; 5,146,426 and 4,774,556. The transistors formed in such trenches may be combined with additional planar devices, as discussed in U.S. Pat. Nos. 4,964,080; 5,078,498. Other memory cells have transistors with a floating body, as discussed in U.S. Pat. No. 5,382,540. Another conventional memory cell, disclosed in U.S. Pat. No. 5,017,977, does not have separated buried bitlines between transistors. Such conventional cells fail to achieve maximum packing density due to non-self-aligned isolation techniques, or require complex processing methods for fabrication, e.g., selective epitaxial growth, which methods are not suitable for large-scale production.
Instead of using the vertical devices of the memory cell 27 as an EPROM, the vertical transistor 15 without a floating gate, in conjunction with a capacitor, can also be used for DRAM applications. FIG. 5 shows a schematic of a typical DRAM cell 100 having a field effect transistor (FET) 105 and a storage capacitor C.sub.s. The gate of the FET 105 acts as the wordline W/L. A bitline B/L is connected to one terminal of the FET 105, which terminal is the source or drain of the DRAM, depending on application. The other DRAM terminal is connected to a storage node 110 of the storage capacitor C.sub.s. The other terminal of the storage capacitor C.sub.s is referred to as a plate 115.
When the FET 105 is turned on by an appropriate signal on the wordline W/L, data is transferred between the bitline B/L and the storage node 110. The conventional one transistor, one capacitor cell 100, shown in FIG. 5, has a theoretical minimum area of 8F.sup.2 for a folded bitline, or 4F.sup.2 for open bitline architecture, shown in FIGS. 6 and 7, respectively.
FIG. 6 shows a top view of a conventional folded bitline DRAM cell 120 having active and passing bitlines B/L.sub.1, B/L.sub.2, respectively, and active and passing wordlines W/L, W/L', respectively. The word and bit lines each have a width F. The bit and word lines are separated from adjacent bit and word lines by a width F. Thus, the area of the folded bitline DRAM cell 120 is 8F.sup.2.
FIG. 7 shows a top view of a conventional open bitline DRAM cell 150, having a bitline B/L and a wordline W/L, each having a length F and being separated from adjacent lines of adjacent cells (not shown) by a length F. Thus, the area of the open bitline DRAM cell 150 is 4F.sup.2.
Due to the need for contact and isolation spacing, in conventional designs that use planar transistors, it is only possible to obtain these minimum cell sizes by creating sub-lithographic features at some level. In addition, if a minimum cell size is to be obtained, it is necessary to reduce the length of the transistor 105 of FIG. 5 as much as possible (down to F). This reduces the gate length. However, shorter gate lengths result in higher leakage currents which cannot be tolerated. Therefore, the voltage on the bitline must be scaled down accordingly. This reduces the charges stored on the storage capacitor C.sub.s, thus requiring a larger capacitance to ensure that the stored charge is sensed correctly, for example, to indicate logic 1 or 0.
Increasing the capacitance of the storage capacitor C.sub.s is achieved by either increasing the capacitor area, or decreasing the effective dielectric thickness located between the capacitor plates. Increasing the capacitor area is becoming more difficult to do without also increasing the cell size, and hence defeating the purpose of shortening the gate in the first place.
Further reducing the dielectric thickness is also difficult, since the thickness of many conventional dielectrics has already reached a minimum practical thickness. To further reduce the dielectric thickness, alternative dielectrics with higher dielectric constant have been explored. While such alternate dielectrics contribute to solving the problem of low charge storage resulting from the decreased bitline voltage, further bitline voltage reduction is limited by the maximum achievable dielectric constant. Accordingly, to further reduce the bitline voltage, an alternative to reducing the gate length of the transistor 105 is necessary.
There is also a need for a memory cell having a proper gate length and capacitor, without increasing the lateral area of the cell.
Conventional one GBit and higher density DRAM cells require several major changes in technology to allow continuing improvements in area occupied per bit without sacrificing the yield. Some options are the use of high permitivity material, such as Barium Strontium Titanate, for storage, the use of vertical transistors with direct tunneling of stored charge in a floating gate region (TRAM--Low Voltage Memory by Tiwari, Hartstein, and Tischler U.S Pat. No. 5,508,543), the use of quantum-effects, or other structures involving use of silicon-on-insulator, vertical transistors, etc.
Major changes in processes, particularly relating to storage of charge, can be significant impediments to fast yield improvement in manufacturing and can even lead to a failure because of the likelihood of unforeseen and unsolvable problems during later stages of product development.